Development of a parallel 3D finite element power semiconductor device simulator

We report on the development of a parallel, scalable and portable 3D finite element power semiconductor device simulator. The simulator is implemented on a Parsytec Supercluster Model 64 which is a medium class 64 transputer MIMD machine and on a four node Power PC based Parsytec X-plorer both in 3L and Parix Fortran. It is based on a spatial decomposition of the simulation domain over an array of processors. This approach minimises the interprocessor communications by reducing the ratio between the bulk and the surface of the partition subdomains. The emphasis is placed on the generation of topologically rectangular FE grids amenable to the domain decomposition approach, on the optimised parallel generation and assembly of the discretization matrices, and on the development of suitable, scalable linear solvers. The advantages of the 3D simulation are highlighted in comparison with 2D simulation results