DocumentCode
2736779
Title
Optimization at runtime on a nanoprocessor architecture
Author
Teller, Justin ; Ozguner, Fusun ; Ewing, Robert
Author_Institution
Dept. of Electr. & Comput. Eng., Ohio State Univ., Columbus, OH
fYear
2008
fDate
10-13 Aug. 2008
Firstpage
882
Lastpage
885
Abstract
Our research addresses the need to efficiently execute and control the increasingly demanding and diverse nature of applications running on embedded systems. We propose optimizing an application at runtime, sharing execution resources between the runtime optimizations and the application. We use the TRIPS processor (developed by the University of Texas at Austin) to demonstrate runtime optimization using speculative slice execution on a nanoprocessor architecture (NA). Preliminary results are promising. Despite the current implementations limitations, we show speedups of 7%/25% (whole application/single task), with larger speedups are possible for future implementations.
Keywords
circuit optimisation; embedded systems; microprocessor chips; TRIPS processor; embedded systems; nanoprocessor architecture; runtime optimization; speculative slice execution; Computer architecture; Dynamic compiler; Intelligent sensors; Parallel processing; Prefetching; Programming profession; Runtime; Unmanned aerial vehicles; Vehicle dynamics; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
Conference_Location
Knoxville, TN
ISSN
1548-3746
Print_ISBN
978-1-4244-2166-4
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2008.4616941
Filename
4616941
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