• DocumentCode
    2737116
  • Title

    Decimal partial product generation architectures

  • Author

    Castellanos, Ivan D. ; Stine, James E.

  • Author_Institution
    Dept. of Comput. & Electr. Eng., Oklahoma State Univ., Stillwater, OK
  • fYear
    2008
  • fDate
    10-13 Aug. 2008
  • Firstpage
    962
  • Lastpage
    965
  • Abstract
    Interest in decimal arithmetic is growing considerably due to its relevance in financial and commercial applications. Previous developments on decimal multiplication focused on sequential implementations due to its complexity. However, recent studies have proposed parallel multipliers to improve performance. This paper clarifies recent techniques for partial product generation and presents implementation results and comparison of available partial product generation architectures. As opposed to previous implementations, which only propose partial product generation designs on paper, this research implements and expands each proposed architecture and addresses its utilization within decimal architectures.
  • Keywords
    digital arithmetic; parallel processing; decimal architectures; decimal arithmetic; decimal multiplication; decimal partial product generation architectures; parallel multipliers; Application software; Computer architecture; Digital arithmetic; Electronic mail; Encoding; Floating-point arithmetic; Hardware; Product design; Table lookup; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
  • Conference_Location
    Knoxville, TN
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4244-2166-4
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2008.4616961
  • Filename
    4616961