Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme

Author

Dia, Kin Hooi ; Zheng, Ruotong ; Ikeda, Makoto ; Asada, Kunihiro

Author_Institution

Dept. of Electron. Eng., Tokyo Univ.

fYear

2005

fDate

Nov. 2005

Firstpage

309

Lastpage

312

Abstract

This paper presents a new footless dual-rail domino circuit that efficiently combines a footless dynamic circuit technique with a robust self-timed precharge scheme for high performance VLSI design. Along with these, the proposed circuit achieves a whole footless dual-rail domino circuit with the use of the proposed separator. A 20-stage NAND chain with fan-out 8 is implemented in 0.15-mum SOI CMOS technology for performance evaluation. Measurement results reveal that the proposed circuit achieves 2.57, 1.72 and 1.12 times speed improvement over the circuit implemented with CPL, the conventional static CMOS and the conventional dynamic DCVSL, respectively

Keywords

CMOS logic circuits; VLSI; logic circuits; logic gates; silicon-on-insulator; 0.15 micron; NAND chain; SOI CMOS; Si; VLSI design; dual-rail domino circuit; footless domino circuit; footless dynamic circuit; self-timed precharging; CMOS logic circuits; CMOS technology; Clocks; Delay; Design engineering; Foot; Inverters; Particle separators; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Solid-State Circuits Conference, 2005

Conference_Location

Hsinchu

Print_ISBN

0-7803-9163-2

Electronic_ISBN

0-7803-9163-2

Type

conf

DOI

10.1109/ASSCC.2005.251727

Filename

4017593