An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design

Author

Gyohten, Takayuki ; Morishita, Fukashi ; Okamoto, Mako ; Dosaka, Katsumi ; Arimoto, Kazutami

Author_Institution

Syst. Core Technol. Div., Renesas Technol. Corp., Itami

fYear

2005

fDate

1-3 Nov. 2005

Firstpage

313

Lastpage

316

Abstract

In this paper, we propose on-chip PVT (process, voltage, and temperature) control system for worst-caseless lower voltage SoC design that consist of the adaptive voltage management (AVM). The proposed AVM accurately controls to set the most suitable voltage level with table look-up method. This PVT control system realizes wide operating margin, DFM function for low voltage SoC. The experimental chip is fabricated on 90nm CMOS process and confirmed the proposed architecture accurately controls the voltage level and the operation margin securing at the lower voltage

Keywords

CMOS integrated circuits; process control; processor scheduling; system-on-chip; table lookup; temperature control; voltage control; 90 nm; CMOS process; DFM function; adaptive voltage management; low voltage SoC; on-chip control system; process-voltage-temperature control system; table look-up; worst-caseless SoC; Character generation; Circuits; Control systems; Oscillators; Random access memory; System-on-a-chip; Temperature control; Temperature dependence; Tuning; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Solid-State Circuits Conference, 2005

Conference_Location

Hsinchu

Print_ISBN

0-7803-9162-4

Electronic_ISBN

0-7803-9163-2

Type

conf

DOI

10.1109/ASSCC.2005.251728

Filename

4017594