Design of a properly scaled 100 nm pseudomorphic HEMT using H2F

In this paper we report on a systematic approach to the design of 100 nm gate length PHEMT using full scale 2D simulation with the recently developed Heterojunction 2D Finite element semiconductor device simulator H2F. The design approach involves four stages: fabrication of pilot devices; validation of the simulator against measured characteristics of these devices; redesign and optimisation of the vertical layer structure based on extensive simulation of 100 nm gate length devices, and finally fabrication of the optimised 100 nm PHEMTs and iterative improvements