Modeling of High-k Gate Stack of Tunnel Barrier in Nonvolatile Memory MOS Structures

We studied effects of nitrogen incorporation in high-k stack gate structures on the program/erase current and retention current for performance improvement of nanoscale nonvolatile memory devices, using a numerical model based on solutions to the Schrodinger-Poisson equations. In particular, comparisons are made for gate current behavior with different tunnel barrier stacks and materials. The changes of the barrier height and dielectric constant in the high-k dielectric stacks enable us to obtain favorable program/erase current and retention current to satisfy the requirements for nonvolatile memory devices. We found that a suitable range of the nitrogen content will enable both the basic requirements for programming and data retention to be satisfied.