DocumentCode
2737300
Title
Heating Effects in Dual-Gate Devices
Author
Goodnick, S.M. ; Raleva, K. ; Vasileska, D.
Author_Institution
Arizona State Univ., Tempe, AZ
fYear
2008
fDate
18-21 Aug. 2008
Firstpage
10
Lastpage
13
Abstract
Heating effects are investigated in dual-gate devices using an in-house thermal particle-based device simulator. Our simulation results demonstrate that the dual-gate structure is advantageous even though there is slightly higher current degradation due to lattice heating compared to conventional single gate structures, since the magnitude of the on-current is 1.5-1.8 times larger in this structure. Thus, one can trade off a slight increase in current degradation due to lattice heating for more current drive.
Keywords
lattice dynamics; semiconductor device models; semiconductor technology; thermal stresses; thermoelectricity; thin film transistors; current degradation; dual-gate devices; dual-gate structure; heating effects; lattice heating; single gate structures; thermal particle based device simulator; CMOS technology; Cost function; Degradation; Heating; High K dielectric materials; Lattices; MOSFETs; Microprocessors; Silicon; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanotechnology, 2008. NANO '08. 8th IEEE Conference on
Conference_Location
Arlington, Texas
Print_ISBN
978-1-4244-2103-9
Electronic_ISBN
978-1-4244-2104-6
Type
conf
DOI
10.1109/NANO.2008.12
Filename
4616994
Link To Document