Digitally controlled phase locked loop with tracking analog-to-digital converter

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter - the key building blocks of digital PLL (DPLL), there is no need for the trade-off between jitter, power consumption and silicon area. The DCPLL was implemented in a 0.18mum CMOS process and the active area is 0.35 mm². The DCPLL consumes 59mW during the normal operation and 984muW during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps rms jitter