Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis

This paper discusses how to improve input capacitance modeling of logic gates for accurate STA (static timing analysis). The input capacitance of logic gates exhibits nonlinear behavior with respect to input signal voltage. Also, its value varies depending on the driving condition of stable inputs as well as loading of multiple-input gates condition of the gate. For the non-linearity issue, the authors propose to use an equivalent capacitance value derived by the integration of input current during partial transition instead of full transition. For the second issue, the authors suggest to consider the minimum capacitance as well as the maximum capacitance, which will eliminate possible errors in the shortest path calculation for hold violation analysis