Energy efficient dual-issue processor for embedded applications

Low cost and low power scalar embedded processors can issue only a single instruction per cycle which results in longer execution time for applications and consequently lower energy efficiency. Superscalar processor that can issue multiple instructions per cycle are more energy efficient than scalar processors, however, they consume more power which is severely limited in embedded systems that operate on small batteries or energy harvesting power sources. In this paper we propose an energy efficient dual-issue embedded processor that can deliver up to 60% improvement in IPC (instruction-per-cycle) performance with less than 20% increase in power consumption compared to a single-issue embedded processor. In contrast to traditional multi-issue embedded processors that use power intensive superscalar techniques to extract instruction-level parallelism from applications, the proposed processor uses simple hardware techniques to resolve instruction scheduling conflicts. The processor is optimized for implementation on low cost FPGAs suitable for power sensitive embedded applications.