Networks-on-chip and Networks-in-Package for High-Performance SoC Platforms

Author

Lee, Kangmin ; Lee, Se-Joong ; Kim, Donghyun ; Kim, Kwanho ; Kim, Gawon ; Kim, Joungho ; Yoo, Hoi-Jun

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon

fYear

2005

fDate

1-3 Nov. 2005

Firstpage

485

Lastpage

488

Abstract

A structured packet-switched networks-on-chip (NoC) is designed and implemented for high-performance heterogeneous SoC design platform. The chip integrates multiprocessors, multiple memories, and other heterogeneous intellectual properties and interconnection with 51mW and 1.6GHz on-chip networks. The NoC adopts a partial activated crossbar, low-energy coding, and low-swing signaling for the power consumption optimization. A network-in-package integrating four NoCs is fabricated in a 676-BGA-type package for larger and scalable systems and demonstrates 2D-image-processing and 3D-graphics applications

Keywords

ball grid arrays; multiprocessing systems; network-on-chip; 1.6 GHz; 2D image processing; 3D graphics; 51 mW; 676-BGA-type package; SoC platforms; multiple memory chip; multiprocessors chip; networks-in-package; networks-on-chip; structured packet-switched networks; Bandwidth; Clocks; Delay; Energy consumption; Intellectual property; Network topology; Network-on-a-chip; Packaging; Power system interconnection; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Solid-State Circuits Conference, 2005

Conference_Location

Hsinchu

Print_ISBN

0-7803-9162-4

Electronic_ISBN

0-7803-9163-2

Type

conf

DOI

10.1109/ASSCC.2005.251783

Filename

4017637