DocumentCode :
2738166
Title :
The Split-Path AND-type Match-line Scheme for Very High-Speed Content Addressable Memories
Author :
Chen, Chia-Cheng ; L, Hung-Yu ; Wang, Jinn-Shyan
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chia-Yi
fYear :
2005
fDate :
1-3 Nov. 2005
Firstpage :
525
Lastpage :
528
Abstract :
The proposed split-path AND-type non-pipelined match-line scheme achieves over 50% search speed improvement compared to the pipelined NOR-type current-saving controlled match-line scheme (Pagiamtzis et al., 2004). The highest world record of 1.6 ns search speed can also be traded for power saving by adopting voltage scaling. When the supply voltage is reduced to a level so that the energy efficiency of both kinds of design is almost equal, the new scheme still has 18% speed improvement over the conventional design. The authors also found that the new design has a smaller area compared to the conventional NOR-type design
Keywords :
integrated memory circuits; logic circuits; logic gates; content addressable memory; nonpipelined match-line; split-path AND-type match-line; voltage scaling; Associative memory; CADCAM; Circuits; Clocks; Computer aided manufacturing; Degradation; Energy consumption; Energy efficiency; Table lookup; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asian Solid-State Circuits Conference, 2005
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-9162-4
Electronic_ISBN :
0-7803-9163-2
Type :
conf
DOI :
10.1109/ASSCC.2005.251793
Filename :
4017647
Link To Document :
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