Title :
An efficient method for modelling VLSI interconnections
Author :
Nelis, H. ; Deprettere, E. ; Dewilde, P.
Author_Institution :
Delft Univ. of Technol., Netherlands
Abstract :
We present an efficient method to model the parasitic capacitance of interconnections in a VLSI circuit. The method is three dimensional, and is based on a combination of the Green´s function method and a recently proposed technique for inverting partially specified, positive definite matrices. It yields a reduced, yet accurate model and requires O(s) time and O(√s) storage, where s is the size of the layout
Keywords :
VLSI; capacitance; circuit CAD; computational complexity; 3D method; Green´s function method; VLSI circuit; computational complexity reduction; matrix inversion; modelling VLSI interconnections; parasitic capacitance of interconnections;
Conference_Titel :
Circuit Theory and Design, 1989., European Conference on
Conference_Location :
Brighton
