Ultra Low-Cost 3.2Gb/s Optical-Rate Reed Solomon Decoder IC Design

Reed-Solomon (RS) code is a widely used forward error correction (FEC) technology to improve the channel impairments in the fiber communication systems. The typical parallel FEC architecture requires huge hardware cost to achieve very-high-speed transmission data rate for the optical systems. This paper presents an ultra low-cost VLSI architecture of RS decoder by using a novel just-in-time folding modified Euclidean algorithm (JIT-FMEA). The JIT-FMEA VLSI architecture can greatly reduce the hardware complexity by about 50% from the fully expanded parallel architecture, while it can achieve very high throughput rate for the 10Gbase-LX4 optical communication system. The proposed RS decoder architecture has been designed and implemented by using 0.18mum CMOS standard cell technology at the supply voltage of 1.8 V. Our design only requires about 21K gates and can achieve the data throughput rate of 3.2Gbit/s at clock frequency of 400MHz