Title :
Group delay as an estimate of delay logic
Author :
Talkhan, I. ; Vlach, J. ; Barby, J. ; Vannelli, A.
Author_Institution :
Waterloo Univ., Ont., Canada
Abstract :
A method is presented for fast calculation of interconnect delay in bipolar of MOS logic networks. It has been established experimentally on many RC lumped networks with arbitrary topologies that the usually defined delay (mid-point for a unit step input), and the group delay at zero frequency, are related by a proportionality constant. Also it has been found that the property remains valid for arbitrarily positioned taps along the network. Derivations give formulas for an efficient numerical method to calculate the group delay and its derivatives with respect to network elements. In connection with mathematical optimization, the method can be used to design taps or branches with prescribed delays
Keywords :
delays; integrated logic circuits; logic design; MOS logic networks; bipolar logic circuits; delay logic; group delay; integrated circuits; interconnect delay; logic design; numerical method;
Conference_Titel :
Circuit Theory and Design, 1989., European Conference on
Conference_Location :
Brighton
