DocumentCode
273853
Title
Calculation of clock path delay and skew in VLSI synchronous systems
Author
Afghahi, M. ; Svensson, C.
Author_Institution
Linkoping Univ., Sweden
fYear
1989
fDate
5-8 Sep 1989
Firstpage
265
Lastpage
269
Abstract
In this paper different clock distribution structures in a synchronous VLSI system are investigated and a new structure is proposed. Then a statistical approach is employed to estimate the variations of the clock path delay due to technological variations. The impact of scaling on clock path delay and its variations is also demonstrated
Keywords
VLSI; clocks; delays; digital integrated circuits; synchronisation; VLSI synchronous systems; clock distribution structures; clock path delay; digital IC; scaling; skew; technological variations;
fLanguage
English
Publisher
iet
Conference_Titel
Circuit Theory and Design, 1989., European Conference on
Conference_Location
Brighton
Type
conf
Filename
51621
Link To Document