A logical timing simulator for CMOS circuits based on an accurate formulation of the propagation delay

A physical model for the evaluation of propagation delay times in CMOS digital circuits has been presented. The procedure to evaluate the delays is easily automatable, in connection with a circuit extractor. Moreover, it allows the definition of logic models for logic cells, which have been implemented in a mixed-level simulator, achieving an accuracy which is similar to the one obtained with circuit-level simulation, with a significant reduction of computer costs. Finally, the piecewise-linear approximation used to model voltage waveforms can also be used for electrical optimization of logic cells and this is illustrated in the case of a buffer structure. Such optimization, together with other design and test constraints, can be easily implemented in a computer program to assist circuit designers