Exploiting parallelism in routing for a hierarchical VLSI design environment

This paper presents research into a novel technique for exploiting parallelism in the automatic routing process for hierarchical VLSI circuit design. A new parallel model which may be used to exploit the parallelism at each stage of the routing process is described. The model has been set up to be as flexible as possible so that the hardware on which it is based can be used to not only speed up the routing process, but also the other phases of the VLSI design cycle. It is often the case when designing hardware accelerators for VLSI design that the need to accelerate other phases of the VLSI design cycle, is ignored. This has often resulted in a very expensive, dedicated piece of hardware which cannot used to speed up other phases of the design process. For the case of routing, the dedicated hardware has been designed to accelerate specifically the maze routing algorithm which is more useful for routing PCBs rather than VLSI designs. The aim of this research is to investigate the possibility of a routing accelerator for VLSI routing based on general purpose processors and a general architecture