DocumentCode :
2739056
Title :
Via2 - Laser Embedded Conductor Technology 2008 The 3rd IMPACT and 10th EMAP Joint Conference
Author :
Huemoeller, Ron
Author_Institution :
Adv. Interconnect Technol., Chandler, AZ
fYear :
2008
fDate :
22-24 Oct. 2008
Firstpage :
110
Lastpage :
113
Abstract :
While semiconductor technology progresses at an alarming rate, typically doubling in functionality every couple of years, the substrate portion of the integrated circuit (I.C.) packaging industry continues to fall further and further behind. This has created a significant technology gap, forcing the semiconductor manufacturers to compensate their chip design by adding more redistribution layers or even worse, adding additional size to the chip itself. There is, therefore, a real need for significant change in manufacturing methods used at the substrate level, to remove this ever widening gap and thus allow the chip manufacturers to continue their path towards reduction in size and cost, while still increasing product functionality. A collaborative effort between Amkor Technology, Unimicron and Atotech, has led to a significant new breakthrough in substrate manufacturing techniques, allowing layer, design feature and format reduction (thus cost reduction) versus current state of the art technologies. This innovative method utilizes laser ablation techniques, together with specially developed plating processes, to form electrical paths for signal propagation embedded within the dielectric, rather than the more conventional conductors on the dielectric layer. This paper is the second part of a two part paper co-authored by Atotech (Dave Baron) and Amkor Technology. This paper describes the opportunity to reduce the number of vias and layers in the substrate, the unique opportunity to optimize electrical performance, and the potential miniaturization in design as a result. A close look at this technology reveals the clear benefits and opportunity for significant gap closure required by the chip packaging industry today.
Keywords :
chip scale packaging; electroplating; integrated circuit design; integrated circuit manufacture; integrated circuit reliability; laser ablation; semiconductor device manufacture; semiconductor device packaging; semiconductor industry; substrates; Amkor Technology; Atotech; Unimicron; chip design; chip manufacturing; design miniaturization; dielectric layer; electrical performance; integrated circuit packaging industry; laser ablation; laser embedded conductor technology; plating process; reliability; semiconductor technology; substrate manufacturing technique; via2 technology; Chip scale packaging; Collaboration; Cost function; Coupling circuits; Dielectric substrates; Integrated circuit packaging; Integrated circuit technology; Manufacturing industries; Semiconductor device manufacture; Semiconductor device packaging;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008. IMPACT 2008. 3rd International
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3623-1
Electronic_ISBN :
978-1-4244-3624-8
Type :
conf
DOI :
10.1109/IMPACT.2008.4783820
Filename :
4783820
Link To Document :
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