Introducing RapidHDL: A New Library to Design FPGA Hardware in Microsoft. Net and Automatically Generate Verilog Netlists

RapidHDL is introduced as a new object oriented hardware description library for C# developers. RapidHDL seeks to speed up FPGA development by applying best practices used in software engineering to increase productivity. Logic is rapidly defined in component classes using a structure of truth-table definitions, sink nodes, source nodes, and pass-through nodes. Hardware simulation co-runs with C# programs, and a linked-list of clock events simulates propagation delays. A standardized testing framework allows the developer to write test benches, hardware, and software in a single language. Algorithms are presented to automatically transform RapidHDL objects to Verilog netlist that can be synthesized by calling 3rd party tools