Performance Evaluation of Flagged Prefix Adders for Constant Addition

The speed of the addition operation can play an important and complicated role in various signal processing algorithms. Parallel prefix adders have been one of the most notable among several designs proposed in the past. The advantage of utilizing these adders is the flexibility in implementing the tree structures based upon on the throughput requirements. Recently, a new technique has been proposed that utilizes the parallel prefix adder but modifies it to yield a new adder capable of performing simple increment and decrement operations. An extension to this adder has also been proposed enhancing the functionality of the same to allow the addition of any arbitrary number. This paper compares the performance of this unique adder design in terms of power, area, and delay by using the Brent-Kung, Kogge-Stone and the Ladner-Fischer tree structures. It also presents the advantage of using these kinds of adders over conventional adder designs to perform the same operation