Title :
Testability enhancement for behavioral descriptions containing conditional statements
Author :
Ockunzzi, Kelly A. ; Papachristou, Christos A.
Author_Institution :
Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
Abstract :
A high-level test synthesis methodology based on BIST is proposed. This methodology targets the conditional if-then-else statements in a behavioral description because such statements can introduce testability problems in the resulting circuit. How well the operations in each branch of a conditional statement can be tested depends on the probability of taking each branch and the quality of the test patterns used in each branch. Behavioral modifications are presented that can resolve these testability issues. Experimental results from three practical examples show that this technique is effective
Keywords :
VLSI; built-in self test; design for testability; digital integrated circuits; high level synthesis; integrated circuit testing; logic testing; probability; BIST; behavioral description; conditional statement; high-level test synthesis; if-then-else; probability; testability; testability enhancement; Automatic test pattern generation; Built-in self-test; Circuit synthesis; Circuit testing; Costs; Design for testability; Design methodology; High level synthesis; Resource management; Very large scale integration;
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-4209-7
DOI :
10.1109/TEST.1997.639619
