Title :
Architecture for Faster RAM Controller Design with Inbuilt Memory
Author :
Wajid, Mohd ; Shashank, S.B.
Author_Institution :
Electron. & Commun. Dept, Jaypee Univ. of Inf. Technol., Solan, India
Abstract :
In this era of fast processors and processors with many cores, there is a requirement for faster and bigger memories. But today the speed of fetching data from memories is not able to match up with speed of processors. So there is the need for a fast memory controller. The responsibility of the controller is to match the speeds of the processor on one side and memory on the other so that the communication can take place seamlessly. Here we have built a memory controller which is specifically targeted for DRAM. Certain novel features were included in the design which could increase the overall efficiency of the controller, such as, searching the internal memory of the controller for the requested data for the most recently used data, instead of going to the RAM to fetch it. The design was implemented on Xilinx ISE till the final simulation and synthesis.
Keywords :
DRAM chips; logic design; microprocessor chips; DRAM; RAM controller design; Xilinx ISE; fast memory controller; fast processors; inbuilt memory; internal memory; Arrays; Capacitors; Clocks; Logic gates; Program processors; Random access memory; DRAM; FPGA; Memory; VLSI;
Conference_Titel :
Computational Intelligence, Communication Systems and Networks (CICSyN), 2010 Second International Conference on
Conference_Location :
Liverpool
Print_ISBN :
978-1-4244-7837-8
Electronic_ISBN :
978-0-7695-4158-7
DOI :
10.1109/CICSyN.2010.38
