Innovative practices session 3C: Advances in silicon debug & diagnosis

Debug and diagnosis using the IEEE 1149.1 TAP has been a useful tool for engineers for some twenty years. The TAP however is limited as it only can provide a single full duplex data stream of 50 to 100mb/s. IEEE 1500 provides higher bandwidth via parallel access to multiple scan-channels however providing physical access to hundreds of pins has become more challenging. This parallel access has little benefit in debug when the SoC is in the system. This presentation focuses on the solution proposed by IEEE P1149.10 which uses a packet protocol over SERDES to access on-chip DFT (instruments) like the TAP but with multi-gigabit SERDES. With the standardization of the IEEE 1149.1-2013 PDL language (Procedural Description Language) which abstracts the TAP, PDL can be used with a higher speed interface as proposed by P1149.10. Use cases of how the proposed standard are shown with benefits for silicon debug.