Thermal Measurement and Simulation of 3D stacked die packages

3D packaging has a great potential for improving circuit performance and degree of integration. It is also an attractive platform for system-in-package solution. 3D packages contain multiple heat sources that produce high power density. Heat dissipation has become a critical issue. However, unlike the single-chip package, for which thermal resistance can be easily defined and measured, the presence of multiple heat sources in multi-chip packages makes the definition of thermal resistance difficult. In addition, multiple chip temperature typically needs to be measured at various power level combinations. In this paper, the thermal performance of two dies stacked plastic ball grid array package (PBGA) has been studied. The junction-to-air thermal resistances are measured by thermal-test-chip method following the JEDEC standard environment. Thermal effects of different power level combination are discussed. In addition, the validity of the superposition technique was evaluated in the determination of junction temperatures with change in power of the various die. Finally, the thermal behavior of packages has been analyzed and validated by computational fluid dynamics (CFD) simulation.