DocumentCode
2740468
Title
SiP Embedded Technology in 12 inch Format
Author
Hu, Dyi-Chung ; Yang, Tsung Jen ; Hu, Ferry
Author_Institution
Technol. Center, ACE Technol., Inc., Hinchu
fYear
2008
fDate
22-24 Oct. 2008
Firstpage
387
Lastpage
389
Abstract
SiP technology has been one of the alternative solutions to system integration. Compare to SoC, SiP has the advantages of integration of dies made from different technologies, e.g. GaAs and Silicon. In some cases, SiP technology may provide faster time to the market and at a lower cost. Despite many research activities, there are few companies actually went into mass production using SiP embedded technology due to lack of standard process and equipment. ACET has developed a SiP embedded structure and process for mass production. Current, ACET has mass production packages using 6" and 8" panel format. In order to further enhance the productivity and efficiency of the SiP embedded technology, going into a larger substrate is a next logical step. In the paper, we shall describe the development of SiP embedded technology in ACET. We also demonstrated successfully of building packages using 12 inch format in our manual line.
Keywords
system-in-package; 12 inch format; SiP embedded technology; mass production; size 12 in; system in package technology; Costs; Electronics packaging; Gallium arsenide; Mass production; Metallization; Silicon; Substrates; Surface reconstruction; Wafer bonding; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008. IMPACT 2008. 3rd International
Conference_Location
Taipei
Print_ISBN
978-1-4244-3623-1
Electronic_ISBN
978-1-4244-3624-8
Type
conf
DOI
10.1109/IMPACT.2008.4783893
Filename
4783893
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