An SOI-based three-dimensional integrated circuit technology

Author

Burns, J. ; McIlrath, L. ; Hopwood, J. ; Keast, C. ; Vu, D.P. ; Warner, Keith ; Wyatt, P.

Author_Institution

Lincoln Lab., MIT, Lexington, MA, USA

fYear

2000

fDate

2000

Firstpage

20

Lastpage

21

Abstract

Three-dimensional integrated circuits (3D-ICs) composed of active circuit layers that are vertically stacked and interconnected are expected to lead to improved logic devices, memories, CPUs, and photosensors (Akasaka, 1986). These circuits require high-density vertical interconnections (3D vias) comparable in aspect ratio to present multilevel vias (Reber and Tielert, 1996). We have constructed and tested 3D ring oscillators and fully parallel 64×64 active pixel sensors using a 3D assembly technology which utilizes SOI wafers to achieve stacking of multiple circuit layers and unrestricted placement of dense 3D vias

Keywords

CMOS image sensors; integrated circuit design; integrated circuit interconnections; photodetectors; silicon-on-insulator; wafer bonding; 3D assembly technology; 3D ring oscillators; 3D vias; 3D-ICs; 4096 pixel; 64 pixel; CPUs; SOI wafers; SOI-based 3D integrated circuit technology; Si-SiO₂; active circuit layers; dense 3D vias; fully parallel active pixel sensors; logic devices; memories; multilevel vias; multiple circuit layer stacking; photosensors; unrestricted via placement; vertical interconnections; vertically interconnected circuit layers; vertically stacked circuit layers; via aspect ratio; Assembly; Circuit testing; Etching; Integrated circuit interconnections; Integrated circuit technology; Inverters; Ring oscillators; Silicon; Three-dimensional integrated circuits; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2000 IEEE International

Conference_Location

Wakefield, MA

ISSN

1078-621X

Print_ISBN

0-7803-6389-2

Type

conf

DOI

10.1109/SOI.2000.892749

Filename

892749