Title :
Ratioed CMOS: a low power high speed design choice in SOI technologies
Author :
Tretz, Christophe R. ; Montoye, Robert K. ; Reohr, William
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Ratioed CMOS gates implemented in a partially-depleted (PD) SOI CMOS technology are usually considered to be high power but end up being both faster and lower power than other circuit implementations, mainly due to the reduced junction capacitance in SOI devices as well as floating-body effects. As an example, a high performance multiplier shifter is 3 to 4 times faster and dissipates 9 times less power than more conventional implementations
Keywords :
CMOS digital integrated circuits; capacitance; high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; multiplying circuits; silicon-on-insulator; PD SOI CMOS technology; SOI devices; SOI ratioed CMOS ICs; SOI technologies; Si-SiO2; circuit implementation; floating-body effects; junction capacitance; low power high speed design; multiplier shifter; partially-depleted SOI CMOS technology; power dissipation; ratioed CMOS gates; CMOS logic circuits; CMOS technology; Capacitance; Circuit noise; Delay effects; Partial discharges; Power dissipation; Signal to noise ratio; Silicon on insulator technology; Switching circuits;
Conference_Titel :
SOI Conference, 2000 IEEE International
Conference_Location :
Wakefield, MA
Print_ISBN :
0-7803-6389-2
DOI :
10.1109/SOI.2000.892753
