Hot electron lifetimes of partially-depleted 0.35 μm SOI NMOS transistors

Author

Brusius, P. ; Liu, S.T. ; Sinha, S. ; Jenkins, W.C.

Author_Institution

Honeywell Inc., Plymouth, MN, USA

fYear

2000

fDate

2000

Firstpage

36

Lastpage

37

Abstract

It has recently been proposed that bulk MOS devices with deep submicron gate lengths and/or at cold temperatures, have an increased tendency for the worst case hot electron condition to exist when V_gs=V_ds (King et al, 2000; Rosenbaum et al, 1999; Wang-Ratkovic et al, 1999). This condition is different from the conventional DC stressing test at the peak substrate current proposed by Takeda and Suzuki and adopted as JEDEC standard (1997). This paper assesses the hot electron lifetime of radiation hard 0.35 μm SOI NMOS transistors under both conditions at temperatures ranging from 77 K to 398 K. These SOI NMOS transistors are fabricated on radiation hardened standard SIMOX substrates

Keywords

MOSFET; SIMOX; carrier lifetime; electric current; hot carriers; radiation hardening (electronics); semiconductor device testing; 0.35 micron; 77 to 398 K; DC stressing test; JEDEC standard; SOI NMOS transistors; Si-SiO₂; bulk MOS devices; cold temperatures; gate length; hot electron lifetime; hot electron lifetimes; partially-depleted SOI NMOS transistors; peak substrate current; radiation hard SOI NMOS transistors; radiation hardened standard SIMOX substrates; worst case hot electron condition; Contracts; Current measurement; Degradation; Electrons; Hot carriers; Laboratories; MOSFET circuits; Physics; Stress measurement; Temperature distribution;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2000 IEEE International

Conference_Location

Wakefield, MA

ISSN

1078-621X

Print_ISBN

0-7803-6389-2

Type

conf

DOI

10.1109/SOI.2000.892757

Filename

892757