Challenges to Crossbar Integration of Nanoscale Two-Terminal Symmetric Memory Devices

Crossbar is the most efficient architecture to organize memory devices into dense, large-scale arrays. Emerging nanotechnology promises two-terminal, symmetric memory devices of superior electrical properties. In this work, however, we show that these two-terminal, symmetric devices impose grave challenges to the crossbar-based memory organization. First, we prove that conventional crossbar organization will not work for such symmetric devices. Second, we propose a revised crossbar organization that does work for such devices. However, diodes or switches must be employed to convert such devices into asymmetrical devices in order to avoid considerable energy cost, which can significantly discount their advantage over conventional asymmetrical devices. Third, we demonstrate that there is significant difference in delay and power consumption for accessing a memory device of different contents, i.e., 0 or 1. Such difference constitutes a performance bottleneck of crossbar- based integration of resistive memory devices.