• DocumentCode
    2740753
  • Title

    Medium-dose SIMOX quality improvement for advanced CMOS applications

  • Author

    Dolan, R. ; Alles, M. ; Anc, M. ; Cordts, B. ; Dunne, J. ; Gindlseperger, M. ; Hornblower, B. ; Jang, T.Y. ; Powell, M. ; Blake, J. ; Nakai, T.

  • Author_Institution
    Ibis Technol. Corp., Danvers, MA, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    46
  • Lastpage
    47
  • Abstract
    Reducing the oxygen dose for implanted (i.e. SIMOX) SOI material, and improving the implantation equipment and process balance, have been pursued in order to meet the requirements of the SIA ITRS (1999), increase yields and reliability of CMOS-SOI circuits, and reduce SOI wafer costs. A manufacturable “medium-dose” SIMOX process optimized for 0.18-0.13 μm CMOS SOI technologies has been developed, yielding BOX and silicon layer thicknesses of ~150 nm and <190 nm respectively. Primary attributes of the material include low particle levels, reduced BOX and silicon defect densities, increased BOX breakdown fields, and reduced surface and interface roughness. These attributes result in improved defect detection capabilities using optical metrology tools, as well as improved BOX and gate oxide integrity
  • Keywords
    CMOS integrated circuits; SIMOX; dielectric thin films; electric breakdown; inspection; integrated circuit measurement; integrated circuit reliability; integrated circuit yield; interface roughness; ion implantation; surface topography; 0.13 to 0.18 micron; 150 nm; 190 nm; BOX breakdown field; BOX defect density; BOX integrity; BOX layer thickness; CMOS SOI technologies; CMOS applications; CMOS-SOI circuit yield; SIMOX process optimization; SOI wafer costs; Si-SiO2; defect detection; gate oxide integrity; implantation equipment; implanted SOI material; interface roughness; manufacturable medium-dose SIMOX process; medium-dose SIMOX wafer quality; optical metrology tools; oxygen dose reduction; particle levels; process balance; reliability; silicon defect density; silicon layer thickness; surface roughness; CMOS process; CMOS technology; Circuits; Costs; Electric breakdown; Manufacturing processes; Materials reliability; Optical materials; Rough surfaces; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2000 IEEE International
  • Conference_Location
    Wakefield, MA
  • ISSN
    1078-621X
  • Print_ISBN
    0-7803-6389-2
  • Type

    conf

  • DOI
    10.1109/SOI.2000.892762
  • Filename
    892762