Analysis and suppression of hysteretic behaviors in PD-SOI CMOS circuits

Author

Higuchi, Hisayulu ; Ikeda, Takashi

Author_Institution

Maebashi Inst. of Technol., Japan

fYear

2000

fDate

2000

Firstpage

60

Lastpage

61

Abstract

Recent advances in ultra-thin silicon-on-insulator (SOI) technology have made partially depleted (PD)-SOI-CMOS a promising candidate for use in high-speed circuits. However, some breakthroughs must still be made, the most important of which would be understanding and control of hysteretic behavior. Some hysteretic characteristics have been analyzed, and some methods to suppress this behavior have been proposed (Assaderaghi et al., 1994; Houston et al., 1998; Maeda et al., 1998; Wei et al., 1998; Pelella et al., 1999). However, the operation-period dependent circuit-delay is not sufficiently understood. In this paper, closed form analysis was used to analyze the operation-period-dependent circuit delay, and the results were confirmed with circuit simulators

Keywords

CMOS integrated circuits; circuit simulation; delays; high-speed integrated circuits; hysteresis; integrated circuit modelling; silicon-on-insulator; PD-SOI CMOS circuits; Si-SiO₂; circuit simulators; closed form analysis; high-speed circuits; hysteretic behavior; hysteretic behavior control; hysteretic behavior suppression; hysteretic characteristics; operation-period dependent circuit-delay; operation-period-dependent circuit delay; partially depleted SOI-CMOS; ultra-thin SOI technology; ultra-thin silicon-on-insulator technology; CMOS technology; Circuit simulation; Delay; Equations; Hysteresis; Impact ionization; Inverters; MOSFET circuits; Silicon on insulator technology; Space vector pulse width modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2000 IEEE International

Conference_Location

Wakefield, MA

ISSN

1078-621X

Print_ISBN

0-7803-6389-2

Type

conf

DOI

10.1109/SOI.2000.892769

Filename

892769