A technology-independent methodology of placement generation for analog circuit

Author

Wong, Wai-chee ; Chan, Philip C.H. ; Law, Wai-on

Author_Institution

Hong Kong Univ. of Sci. & Technol., Hong Kong

fYear

1999

fDate

18-21 Jan 1999

Firstpage

141

Abstract

An automatic placement system with emphasis on technology independent methodology and device matching consideration for analog layout design is presented. A novel optimization approach based on circuit partitioning, simulated annealing and a branch-and-bound algorithm is proposed to solve the placement problem. The move set used to generate perturbations for annealing is capable of arriving at any topological placement. The branch-and-bound is modified to take circuit performance into consideration. Results of two silicon proven designs generated by the system demonstrate an 8X cycle time reduction as compared to a manual approach

Keywords

analogue integrated circuits; circuit layout CAD; circuit optimisation; integrated circuit layout; network topology; simulated annealing; analog circuit; analog layout design; automatic placement system; branch/bound algorithm; circuit partitioning; cycle time reduction; device matching; optimization approach; placement generation; simulated annealing; technology-independent methodology; topological placement; Analog circuits; Circuit optimization; Circuit simulation; Costs; Degradation; Integer linear programming; Partitioning algorithms; Routing; Silicon; Simulated annealing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Conference_Location

Wanchai

Print_ISBN

0-7803-5012-X

Type

conf

DOI

10.1109/ASPDAC.1999.759980

Filename

759980