DocumentCode
2741017
Title
Node sampling technique to speed up probability-based power estimation methods
Author
Choi, Hoon ; Kim, Hansoo ; Park, In-Cheol ; Hwang, Seung Ho ; Kyung, Chong-Min
Author_Institution
Dept. of Electr. Eng., Korea Adv. Energy Res. Inst., Daejeon, South Korea
fYear
1999
fDate
18-21 Jan 1999
Firstpage
157
Abstract
We propose a new technique called node sampling to speed up the probability-based power estimation methods. It samples and processes only a small portion of total nodes to estimate the power consumption of a circuit. It is different from the previous speed-up techniques for probability-based methods in that the previous techniques reduce the processing time for each node while our method reduces the number of nodes actually processed. In addition, it is also different from the previous statistical sampling simulation techniques for simulation-based methods in that the previous methods sample the input vectors while our method samples the nodes in the network. The experimental results are very encouraging. The proposed method shows on the average more than 80% and 60% reductions of simulation run time under 20% and 5% error bounds, respectively
Keywords
VLSI; circuit simulation; integrated circuit design; parameter estimation; probability; IC design; VLSI design; node sampling technique; power consumption; probability-based power estimation methods; simulation run time reduction; speed-up technique; Binary decision diagrams; Circuit simulation; Circuits and systems; Computational modeling; Delay effects; Energy consumption; Portable computers; Sampling methods; Switching circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location
Wanchai
Print_ISBN
0-7803-5012-X
Type
conf
DOI
10.1109/ASPDAC.1999.759984
Filename
759984
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