A limited connectivity switched capacitor analogue neural processing circuit with digital storage of nonbinary input weights

In order to implement large neural networks in silicon, it is desirable to reduce both the connectivity and the precision requirements. However, there exists little knowledge about how such networks might perform on the sorts of pattern classification tasks to which they might be applied. Two distinct parts of an experimental investigation into neural networks, based on elements with limited connectivity and employing input variable weighting which approximates to continuous valued control, are described. Firstly, an analogue VLSI implementation was designed from a defined functional description. From this, it was possible to quantify the compromises in electrical performance necessary to achieve an efficient and compact circuit. As the design was taken to mask level, it also gave a clear indication of the functional density per chip. Secondly, the behaviour of such networks was investigated using a functional model of the processing element circuit level behaviour. This phase supports some of the initial design decisions, and shows improvements to be made in a second iteration