An implementation of fully analogue sum-of-product neural models in VLSI

Neural networks that use digital or partly digital processing units have a restricted set of applications, and also are constrained by the set of learning rules that can be used with them. Analogue networks have a greater flexibility in their learning algorithms and a larger domain of problems which they can solve. The flexibility of an analogue output capability can also be used to give an idea of the certainty or accuracy of results. The design was fabricated using a 2 μm CMOS fabrication process. This provides a relatively low cost, easily available medium for research and would allow easy fabrication of any products arriving from this research on industrial processes. The implementation uses pulse frequency modulation to achieve analogue input and output capability, and uses a pulse width modulation method to realise the synaptic multiplication component. This pulse coding technique reduces the size and complexity of the synaptic multiplier which has to be repeated for each neural connection in the network. This greatly reduces the silicon area required for the architecture