DocumentCode
2741316
Title
Watermarking layout topologies
Author
Charbon, Edoardo ; Torunoglu, Ilhami
Author_Institution
Cadence Design Syst. Inc., San Jose, CA, USA
fYear
1999
fDate
18-21 Jan 1999
Firstpage
213
Abstract
Watermarking is a technique currently being developed to effectively protect intellectual property of various types. In this paper a formalization of the watermarking problem is presented in the context of IC physical design. A class of algorithms is proposed for implanting arbitrary codes in the inherent structure of layout topologies. Similarly, a method is given to reconstruct the original watermark for a given design. The concepts of robustness against forgery and theft tracking are analyzed in light of the proposed algorithms. Examples show the suitability of the approach
Keywords
copy protection; cryptography; image coding; industrial property; integrated circuit layout; network topology; IC physical design; active watermarking; arbitrary codes; class of algorithms; intellectual property; layout topologies; passive watermarking; robustness against forgery; theft tracking; watermarking problem; Algorithm design and analysis; Circuit synthesis; Circuit topology; Explosions; Forgery; Intellectual property; Phase detection; Protection; Robustness; Watermarking;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location
Wanchai
Print_ISBN
0-7803-5012-X
Type
conf
DOI
10.1109/ASPDAC.1999.759998
Filename
759998
Link To Document