Evaluation of circuit approaches in partially depleted SOI-CMOS

Author

Das, Koushik K. ; Brown, Richard B.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

fYear

2000

fDate

2000

Firstpage

98

Lastpage

99

Abstract

Partially depleted (PD) SOI has a number of nonideal effects due to the floating body: parasitic bipolar action, history dependent threshold voltage and logic delays, and the `kink´ effect. One must design around these effects in digital circuits so as to avoid circuit malfunction. This paper reviews the circuit design issues in PD-SOI CMOS technology. Realistic circuits from our design vehicle, a 32-bit PowerPC fixed-point execution unit, are included in the evaluation of the various circuit design alternatives. HSPICE simulations have been performed using a 0.25 μm SOI process and a bulk process

Keywords

CMOS digital integrated circuits; SPICE; delays; fixed point arithmetic; integrated circuit design; microprocessor chips; silicon-on-insulator; 0.25 micron; 32 bit; HSPICE simulations; PD SOI; PD-SOI CMOS technology; PowerPC fixed-point execution unit; SOI process; Si-SiO₂; bulk process; circuit design; circuit design issues; circuit malfunction; design vehicle; digital circuit design; floating body effects; history dependent logic delays; history dependent threshold voltage; kink effect; nonideal effects; parasitic bipolar action; partially depleted SOI-CMOS; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Delay; Logic circuits; Logic design; Parasitic capacitance; Timing; Vehicle dynamics;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2000 IEEE International

Conference_Location

Wakefield, MA

ISSN

1078-621X

Print_ISBN

0-7803-6389-2

Type

conf

DOI

10.1109/SOI.2000.892788

Filename

892788