DocumentCode :
2741440
Title :
Model order reduction of large circuits using balanced truncation
Author :
Rabiei, Payam ; Pedram, Massoud
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
1999
fDate :
18-21 Jan 1999
Firstpage :
237
Abstract :
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order of circuits before circuit-level simulation. In contrast to Pade-based algorithms which match the reduced order system with original system in some given frequencies, balanced realization based model algorithms provide a nearly optimal matching over all frequencies. Hence the balanced realization method produces stable and more accurate results compared to the Pade-based algorithms for model reduction. In addition given an upper bound for error, it is possible to compute the minimum degree for the reduced order model a priori. A numerically efficient method for balanced truncation of large circuits using the Arnoldi algorithm is presented and experimental results are reported
Keywords :
VLSI; circuit layout CAD; circuit simulation; integrated circuit layout; state-space methods; Arnoldi algorithm; IC layout; VLSI; balanced truncation; circuit-level simulation; error upper bound; model order reduction; nearly optimal matching; numerically efficient method; Capacitors; Circuit simulation; Computational modeling; Equations; Frequency; Inductors; Integrated circuit interconnections; Reduced order systems; Resistors; Transmission line matrix methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location :
Wanchai
Print_ISBN :
0-7803-5012-X
Type :
conf
DOI :
10.1109/ASPDAC.1999.760004
Filename :
760004
Link To Document :
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