Power consumption in XOR-based circuits

Author

Ye, Yibin ; Roy, Kaushik ; Drechsler, Rolf

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

1999

fDate

18-21 Jan 1999

Firstpage

299

Abstract

The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using different delay models such as unit delay, fanout delay, and random delay in power estimation of XOR dominated logic. Due to different possible implementations of XOR gate, we model the XOR gate as a basic gate and a complex static CMOS gate, respectively. Power dissipation due to (charging and discharging) internal node capacitances is also considered

Keywords

CMOS logic circuits; delay estimation; design for testability; integrated circuit design; logic design; logic gates; power consumption; CMOS gate; XOR dominated logic; XOR gates; charging; delay models; discharging; fanout delay; internal node capacitances; power consumption; power dissipation; power estimation; random delay; static CMOS gate; testability; unit delay; CMOS logic circuits; Capacitance; Circuit synthesis; Circuit testing; Delay estimation; Energy consumption; Logic circuits; Logic design; Power dissipation; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Conference_Location

Wanchai

Print_ISBN

0-7803-5012-X

Type

conf

DOI

10.1109/ASPDAC.1999.760018

Filename

760018