A VLSI and WSI systolic architecture for multilayer feed-forward networks of arbitrary size

Summary form only given, as follows. The authors discuss a systolic architecture for the VLSI and WSI (wafer scale integration) implementation of multilayer feedforward networks in which the simplicity of the processing elements facilitates their integration. This architecture permits parallel and/or cascade connections of multiple base modules without the need of additional hardware. This way, interconnecting many chips for a complete system, one can implement structures with a large number of layers and neurodes per layer and their performance can be improved