SOI wafer selection for CCD/SOI-CMOS technology

We have developed a process that monolithically integrates fully depleted SOI CMOS (FDSOI) with high-performance CCD image sensors (Suntharalingam et al, 2000). This integrated technology enables charge-coupled devices (CCDs) to be in close proximity to, yet isolated from, FDSOI circuits. This approach exploits both the advantages of FDSOI (fast, low-power CMOS with potentially enhanced radiation performance) and those of CCDs (high quantum efficiency, low noise, and architectural flexibility). This 3.3 V, 0.3 μm CCD/FDSOI-CMOS technology thus enables fabrication of low-power, compact imaging systems. Material requirements for CCD imagers are perhaps the most stringent of any device and require special attention to the quality of the bulk or handle wafer (Gregory et al, 1996). We report here characterization of various SOI handle wafers for use in fabrication of bulk imaging devices