High frequency input isolation circuit for asynchronous CMOS macros in PD/SOI technology

The circuit techniques presented in this paper are particularly useful for self-resetting CMOS (SRCMOS) (Henkels et al, 1999) designs in a partially depleted (PD) SOI technology, where pulse width alignment and control becomes much more difficult due to the hysteresis effect in floating body devices. Static and dynamic input isolation circuits are provided at the interface of the macro boundary in asynchronous CMOS design to render the input pulses within the specification. The technique does not require handshaking or interlock signals and is shown to improve the robustness of SRCMOS macros, especially in PD/SOI technology. The robustness of the circuit is demonstrated across a wide range of temperatures, L_effs and operating frequencies over 3 GHz with a minimum input pulse width of 0.2 ns