Combining GAs and symbolic methods for high quality tests of sequential circuits

Author

Keim, Martin ; Drechsler, Nicole ; Becker, Bernd

Author_Institution

Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany

fYear

1999

fDate

18-21 Jan 1999

Firstpage

315

Abstract

A symbolic fault simulator is integrated in a Genetic Algorithm (GA) environment to perform Automatic Test Pattern Generation (ATPG) for synchronous sequential circuits. In a two phase algorithm, test length and fault coverage as well are optimized. However, there are circuits with bad random testability properties, that are also hard to test using genetically optimized test patterns. Thus, deterministic aspects are included in the GA environment to improve fault coverage. Experiments demonstrate that tests with higher fault coverages and considerably shorter test sequences than in previously presented approaches are obtained

Keywords

automatic test pattern generation; fault simulation; genetic algorithms; integrated circuit testing; integrated logic circuits; sequential circuits; symbol manipulation; ATPG; deterministic aspects; fault coverage optimization; genetic algorithm environment; genetically optimized test patterns; high quality tests; symbolic fault simulator; symbolic methods; synchronous sequential circuits; test length optimization; two-phase algorithm; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Logic testing; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Conference_Location

Wanchai

Print_ISBN

0-7803-5012-X

Type

conf

DOI

10.1109/ASPDAC.1999.760022

Filename

760022