DocumentCode :
2741882
Title :
Realization of regular ternary logic functions using double-rail logic
Author :
Iguchi, Yoshinori ; Matsuura, Munehiro ; Sasao, Tsutomu ; Iseno, Atsumu
Author_Institution :
Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
fYear :
1999
fDate :
18-21 Jan 1999
Firstpage :
331
Abstract :
In logic simulation, we often have to evaluate logic functions in the presence of unknown inputs. However, the naive method often produces incorrect values. In these cases, we can produce correct values by evaluating regular ternary logic functions instead of switching functions. This paper proposes a realization of regular ternary logic functions by using double-rail logic. This implementation requires O(2 n/n) logic cells, and O(n) time to simulate an n-variable logic function. We showed an FPGA realization that is about 100 times faster than software simulation
Keywords :
cellular arrays; computational complexity; field programmable gate arrays; logic simulation; switching functions; ternary logic; FPGA realization; O(2n/n) logic cells; double-rail logic; logic functions; logic simulation; n-variable logic function; regular ternary logic functions; switching functions; unknown inputs; Binary decision diagrams; Boolean functions; Computational modeling; Computer science; Computer simulation; Data structures; Field programmable gate arrays; Hardware; Logic functions; Multivalued logic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location :
Wanchai
Print_ISBN :
0-7803-5012-X
Type :
conf
DOI :
10.1109/ASPDAC.1999.760026
Filename :
760026
Link To Document :
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