Title :
Design of cache test hardware on the HP PA8500
Author :
Brauch, Jeff ; Fleischman, Jay
Author_Institution :
Microprocessor Lab., Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
There are many difficulties inherent in the testing of large on-chip caches. This paper presents some of these problems and provides motivation for solving them. After the motive has been established, the techniques used to test the PA8500 on-chip caches are described. This is followed by a detailed explanation of the test hardware, and an example of how it is used
Keywords :
automatic testing; cache storage; computer testing; design for testability; integrated circuit testing; logic testing; microprocessor chips; redundancy; HP PA8500; PA8500; cache architecture; cache test hardware; direct access test; on-chip caches; redundancy control; Computer architecture; Hardware; Microprocessors; Packaging; Pins; Production; Read-write memory; Registers; Silicon; System testing;
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-4209-7
DOI :
10.1109/TEST.1997.639629
