• DocumentCode
    2742054
  • Title

    Constraint-based test pattern generation at the Register-Transfer Level

  • Author

    Viilukas, Taavi ; Raik, Jaan ; Jenihhin, Maksim ; Ubar, Raimund ; Krivenko, Anna

  • Author_Institution
    Tallinn Univ. of Technol., Tallinn, Estonia
  • fYear
    2010
  • fDate
    14-16 April 2010
  • Firstpage
    352
  • Lastpage
    357
  • Abstract
    The paper introduces a novel constraint-based automated test pattern generator for Register-Transfer Level (RTL) designs. The tool combines test path constraint activation with a constraint solver. First, a deterministic algorithm that extracts constraints for activating test paths at RTL is applied. Subsequently, a constraint solving package ECLiPSe is used for assembling the tests. Experiments on ITC99 and HLSynth92/95 benchmarks show that the proposed deterministic method offers short run times. In particular, it provides increased fault coverage for hard-to-test designs with respect to earlier, semiformal, approaches.
  • Keywords
    automatic test pattern generation; decision diagrams; sequential circuits; ECLiPSe; HLSynth92/95 benchmarks; ITC99 benchmarks; constraint solver; constraint-based test pattern generation; register-transfer level designs; test path constraint activation; Assembly; Automatic test pattern generation; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Engines; Packaging; Sequential circuits; Test pattern generators; Register-transfer level; automated test pattern generation; constraint satisfaction problems; decision diagrams;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on
  • Conference_Location
    Vienna
  • Print_ISBN
    978-1-4244-6612-2
  • Type

    conf

  • DOI
    10.1109/DDECS.2010.5491752
  • Filename
    5491752