Test pattern generation for the combinational representation of asynchronous circuits

Author

Dobai, Roland ; Gramatová, Elena

Author_Institution

Inst. of Inf., Slovak Acad. of Sci., Bratislava, Slovakia

fYear

2010

fDate

14-16 April 2010

Firstpage

323

Lastpage

328

Abstract

In this paper we propose a new deterministic automatic test pattern generator (ATPG) for the stuck-at faults of the combinational representation (CR) of asynchronous sequential digital circuits (ASDCs). The modified FAN algorithm is applied to this CR to generate the test patterns. The FAN was extended to handle the complex gates and to be able to work with the CR of ASDCs. The ATPG was tested over a set of benchmark circuits. The test patterns from the presented ATPG will be used in the future to generate the sequence of test patterns for the ASDCs.

Keywords

asynchronous circuits; asynchronous sequential logic; automatic test pattern generation; combinational circuits; fault diagnosis; logic testing; asynchronous sequential digital circuits; benchmark circuits; combinational representation; deterministic automatic test pattern generator; modified FAN algorithm; Asynchronous circuits; Automatic test pattern generation; Chromium; Circuit faults; Circuit testing; Digital circuits; Hazards; Logic; Test pattern generators; Variable speed drives;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on

Conference_Location

Vienna

Print_ISBN

978-1-4244-6612-2

Type

conf

DOI

10.1109/DDECS.2010.5491759

Filename

5491759