Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOS

Two memory elements, or latches, are introduced. They are similar in functionality to widely used NOR- and NAND-based crosscoupled latches, but unlike the traditional latces they do not risk to produce stable states where Q and Q´ have identical binary values. The suggested solutions are built from two inverters and one minority-3 gate. Monte Carlo simulations in 90 nm CMOS are used to demonstrate that the circuits may maintain the digital abstraction under mismatch and process variations for a supply voltage down to 140 mV at 20 degrees C and 100 nm gate lengths. Chip measurements are included. Reliability issues for low fan-in threshold gates might favour them over some traditional Boolean implementations, which may contribute to increased use of CMOS threshold gates, if proven.